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aSC7512
DIGITAL TEMPERATURE SENSOR WITH INTEGRATED FAN CONTROL
Fully Released Specification Product Description
The aSC7512 has a two wire digital interface compatible with SMBus 2.0. Using a 10-bit - ADC, the aSC7512 measures the temperature of a remote diode connected transistor as well as its own die. Using temperature information from these two zones, an automatic fan speed control algorithm is employed to minimize acoustic impact while achieving recommended CPU temperature under varying operational loads. To set fan speed, the aSC7512 has a pulse width modulation (PWM) output that is controlled by one of two temperature zones. Both high- and low-frequency PWM ranges are supported. The aSC7512 also includes a digital filter that can be invoked to smooth temperature readings for better control of fan speed and minimum acoustic impact. The aSC7512 has a tachometer input to measure fan speed or alternatively, an alert pin that may be triggered by exceeding a temperature limit setting. Limit and status registers for all measured values are included to alert the system host that any measurements are outside of programmed limits.
PRODUCT SPECIFICATION
Measurement System
Temperature: * 0.25C resolution, 1C accuracy on remote diode * 0.25C resolution, 3C accuracy on local sensor * Extended temperature measurement range on remote sensor -55C to +125C using or 2's complement coding. Fan Tachometer: * 16-bit count of 90KHz clock periods Limit alarms for all measured values
Applications
* * * Desktop Computers - Motherboards and Graphics Cards Laptop Computers Microprocessor based equipment (e.g. Basestations, Routers, ATMs, Point of Sales)
Features
* * * * * * * * * * 2-wire, SMBus 2.0 compliant, serial digital interface 10-bit -ADC Monitors internal and remote thermal diodes Programmable autonomous fan control based on temperature readings Noise filtering of temperature reading for fan control 0.25C digital temperature sensor resolution PWM fan speed control output for 2-, 3- or 4-wire fans. Provides high and low PWM frequency ranges Fan tachometer input or ALERT output 8-lead MSOP or SOIC package
Connection Diagram
VDD D+ DPWM
1 2
8 7
SMBCLK SMBDAT TACH / ALERT GND
aSC7512
3 6
4
5
Ordering Information
Part Number aSC7512D8 ASC7512M8 Package 8-lead SOIC 8-lead MSOP Temperature Range and Operating Voltage -40C to +125C, 3.3V -40C to +125C, 3.3V Marking aSC7512 Ayww 7512 Ayww How Supplied 2500 units Tape & Reel 2500 units Tape & Reel
Ayww - Assembly site, year, workweek
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aSC7512
Block Diagram
SMBus Interface SMBDAT SMBCLK
PWM
Fan PWM Control Register
ID Registers Fan Speed TACH / ALERT
Pin MUX
Limit Registers Limit Comparators Status Registers
Tach Signal Conditioner
Address Pointer
Fan T-min, T-range & T-Hyst Configuration Register Spike Smoothing
D+ DInternal Sensor
Diode Signal Conditioning & Analog Mux
ADC
Digital Filter
Fan Control Registers Fan Characteristic Registers
Bandgap Reference
Fan Speed Configuration
Figure 1 Block Diagram
Pin Descriptions
Symbol SMBus SMBDAT SMBCLK VDD Pin 7 8 1 Type Digital I/O (Open-Drain) Digital Input POWER Name and Function/Connection System Management Bus Data. Open-drain output. 5V tolerant, SMBus 2.0 compliant. System Management Bus Clock. Tied to Open-drain output. 5V tolerant, SMBus 2.0 compliant. +3.3V pin. Can be powered by +3.3V Standby power if monitoring in low power states is required. This pin should be bypassed with a 0.1F capacitor in parallel with 100pF Ground for all analog and digital circuitry. Positive input (current source) from the remote thermal diode serves as the positive input into the A/D. Connected to the anode of a CPU thermal diode or the base-collector of a diode connected MMBT3904 NPN transistor. Negative input (current sink) from the remote thermal diode serves as the negative input into the A/D. Connected to cathode of a CPU thermal diode or the emitter of a diode connected MMBT3904 NPN transistor. Input for monitoring tachometer output of fan (default) or
ALERT output selectable by configuration register 09h, bit 5.
Power
GND D+ Remote
5 2
GROUND Remote Thermal Diode Positive Input
D-
3
Remote Thermal Diode Negative Input Digital Input / Digital Open-Drain Output Digital Open-Drain Output
Fan / Alert
TACH /
ALERT
6 4
PWM
Fan speed control, Pulse Width Modulated.
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aSC7512
Absolute Maximum Ratings1
Parameter Supply Voltage, VDD Voltage on Any Digital Input or Output Pin Voltage on Remote + Current on Remote Input Current on Any Pin2 Package Input Current2 Package Dissipation at TA = 25C Storage Temperature ESD4 Human Body Model Machine Model Rating -0.5V to 6.0V -0.5V to 6.0V -0.5V to (VDD + 0.50V) 1mA 5mA 20mA See (Note 3) -65C to +150C 2500 V 250 V
Notes: 1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress ratings only; functional operation at or above these limits is not implied. 2. When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VDD), the current at that pin should be limited to 5mA. The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four. Parasitic components and/or ESD protection circuitry are present on the aSC7512 pins. Care should be taken not to forward bias the parasitic diode present on pins D+ and D-. Doing so by more than 50mV may corrupt temperature measurements. 3. Thermal resistance junction-to-ambient when attached to a double-sided printed circuit board with 1oz. foil is TBDC/W 4. Human Body Model: 100pF capacitor discharged through a 1.5k resistor into each pin. Machine Model: 200pF capacitor discharged directly into each pin.
Operating Ratings1
Parameter aSC7512 Operating Temperature Range Remote Diode Temperature Range Supply Voltage (3.3V nominal) All Other Inputs Typical Supply Current Rating -40C TA +125C -55C TD +125C +3.0V to +3.6V -0.05V to VDD + 0.05V TBDmA
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aSC7512
DC Electrical Characteristics5
The following specifications apply for VDD = 3.3V, and all analog input source impedance Rs = 50 unless otherwise specified in conditions. Boldface limits apply for TA = TJ over TMIN to 85C; all other limits TA = TJ = 25C. TA is the ambient temperature of the aSC7512; TJ is the junction temperature of aSC7512; TD is the remote thermal diode junction temperature. Specifications subject to change without notice Parameter POWER SUPPLY CHARACTERISTICS Supply Current Power-On Reset Threshold Voltage TEMPERATURE TO DIGITAL CONVERTER CHARACTERISTICS Resolution Local Sensor Accuracy6 -40C T A +100C, 3V V D D 3.6V 0C T A +100C, -55CTD +125C, 3VVDD3.6V -40C T A +120C, -55CTD +125C, 3VVDD3.6V IDS High Level Low Level 96 6 16 IOL VOL VOL IOH VIH VIL VHYST 300 VOL = 0.4V IOUT = +8mA IOUT = +4mA VOUT = V+ 2.1 0.8 0.1 8 0.4 mA (min) V (max) V (max) A(max) V (min) V (max) mV 0.25 10 1 1 3 2 C Bits C C Converting, Interface and Fans Inactive, Peak Current Converting, Interface and Fans inactive, Average Current 1.6 1.8 0.5 2.8 3.5 mA(max) mA V Conditions Min Typ Max Units
Remote Sensor Accuracy
7
3
C A A
External Diode Current Source External Diode Current Ratio
DIGITAL OPEN-DRAIN OUTPUT: PWM Logic Low Sink Current Logic Low Level Logic Low Output Voltage High Level Output Current Logic Input High Voltage Logic Input Low Voltage Logic Input Hysteresis Voltage DIGITAL INPUTS: ALL Logic Input High Voltage Logic Input Low Voltage Logic Input Threshold Voltage Logic High Input Current Logic Low Input Current Digital Input Capacitance VIH VIL VTH IIH IIL CIN VIN = V+ VIN = GND 1.5 0.005 -0.005 20 10 -10 2.1 0.8 V (min) V (max) V A(max) A(max) pF
SMBUS OPEN-DRAIN OUTPUT: SMBDAT 0.4 10
SMBUS INPUTS: SMBCLK, SMBDAT
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aSC7512
AC Electrical Characteristics
The following specifications apply for VDD = 3.3V unless otherwise specified in conditions. Boldface limits apply for TA = TJ over TMIN to 85C; all other limits TA = TJ = 25C. Parameter TACHOMETER Fan Full-Scale Count Fan Counter Clock Frequency Fan Count Conversion Time FAN PWM OUTPUT Low-Frequency Range Frequency Range High-Frequency Range Duty-Cycle Range Duty-Cycle Resolution (8-bits) Spin-Up Time Interval Range 0.3906 0 4000 10 94 22.5 30 0 to 100 Hz Hz kHz kHz %(max) %/count ms ms 90 0.7 1.46 65535 (max) kHz sec(max) Conditions Min Typ Max Units
Logic Electrical Characteristics
(TA = 25 C, VDD = 3.3V unless otherwise noted) Parameter Input Voltage Logic High Input Voltage Logic Low Output Voltage Logic Low ( ALERT ) Output Low Sink Current ( ALERT ) Input Leakage Current SMBus Output Sink Current SMBus Logic Input Current Output Leakage Current Output Transition Time Input Capacitance Symbol VIH VIL VOL IOL IIN IOL IIH, IIL IOH tF CIN VOH = VDD = 5.5V CL= 400pF, IOL = -3mA All Digital Inputs Conditions 3V V D D 3.6V 3V V D D 3.6V VDD=5V, IOL= -6mA
ALERT forced to 0.4V
Min 2.1
Typ
Max 0.8 0.4
Units V V V mA
6 1.0 6 -1 0.1 +1 1 250 5
VIN = 0V or 5.5V, -40C T A +125C TA = 25 C, VOL = 0.6V
A mA A A ns pF
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aSC7512
Serial Port Timing
(TA = 25 C, VDD = 3.3V unless otherwise noted, Guaranteed by design, not production tested) Parameter SCL Operating Frequency SCL Clock Transition Time SCL Clock Low Period SCL Clock High Period Bus free time between a Stop and a new Start Condition Data in Set-Up to SCL High Data Out Stable after SCL Low SCL Low Set-up to SDA Low (Repeated Start Condition) SCL High Hold after SDA Low (Start Condition) SDA High after SCL High (Stop Condition) Time in which aSC7512 must be operational after a power-on reset Symbol fSCL tT:LH , tT:HL tLOW tHIGH tBUF tSU:DAT tHD:DAT tSU:STA tHD:STA tSU:STO tPOR 1.3 0.6 1.3 100 300 600 600 600 500 50 Min Typ Max 400 300 Units kHz ns s s s ns ns ns ns ns ms
SCL
tHD:STA tSU:DAT
tSU:STA tSU:STO
SDA
tBUF tLOW tHIGH tT:LH 90 10 tT:HL 90 10
SCL SDA
Data Out
tHD:DAT
5. These specifications are guaranteed only for the test conditions listed. 6. The accuracy of the aSC7512 is guaranteed when using the thermal diode of a processor or any thermal diode with a non-ideality of 1.008 and internal series resistance of 3.52. When using a 2N3904 type transistor as a thermal diode the error band will be typically shifted depending on transistor characteristics. 7. Accuracy (expressed in C) = Difference between the aSC7512 reported output temperature and the temperature being measured. Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal power dissipation of the aSC7512 and the thermal resistance. See (Note 3) for the thermal resistance to be used in the self-heating calculation. 8. Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the aSC7512's SMBus state machine, therefore setting the SMBDAT pin to a high impedance state.
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aSC7512
Control Communication
SMBus
The aSC7512 is compatible with devices that are compliant to the SMBus 2.0 specifications. More information on this bus can be found at http://www.smbus.org/. Compatibility of SMBus2.0 to other buses is discussed in the SMBus 2.0 specification.
Slave Address
aSC7512 is designed to be used primarily in desktop systems that require only one monitoring device. The SMBus slave address is fixed at 58 hex (x 1 0 1 1 0 0 0 binary).
Writing to and Reading from the aSC7512
All read and write operations must begin with a start condition generated by the master device. After the start condition, the master device must immediately send a slave address (7-bits) followed by a R/ W bit. If the slave address matches the address of the aSC7512, it sends an ACK by pulling the SDA line low for one clock. Read or write operations may contain one- or two-bytes. See Figures 2 through 6 for timing diagrams for all aSC7512 operations.
General Operation
Writing to and reading from the aSC7512 registers is accomplished via the SMBus-compatible two-wire serial interface. SMBus protocol requires that one device on the bus initiate and control all read and write operations. This device is called the "master" device. The master device also generates the SCL signal that is the clock signal for all other devices on the bus. All other devices on the bus are called "slave" devices. The aSC7512 is a slave device. Both the master and slave devices can send and receive data on the bus. During SMBus operations, one data bit is transmitted per clock cycle. All SMBus operations follow a repeating nine clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device. Note that there are no unused clock cycles during any operation-- therefore there must be no breaks in the stream of data and ACKs / NACKs during data transfers. For most operations, SMBus protocol requires the SDA line to remain stable (unmoving) whenever SCL is high -- i.e. any transitions on the SDA line can only occur when SCL is low. The exceptions to this rule are when the master device issues a start or stop condition. Note that the slave device cannot issue a start or stop condition.
Setting the Register Address Pointer
For all operations, the address pointer stored in the address pointer register must be pointing to the register address that is going to be written to or read from. This register's content is automatically set to the value of the first byte following the R/ W bit being set to 0. After the aSC7512 sends an ACK in response to receiving the address and R/ W bit, the master device must transmit an appropriate 8-bit address pointer value as explained in the Registers section of this data sheet. The aSC7512 will send an ACK after receiving the new pointer data. The register address pointer set operation is illustrated in Figure 2. If the address pointer is not a valid address the aSC7512 will internally terminate the operation. Also recall that the address register retains the current address pointer value between operations. Therefore, once a register is being pointed to, subsequent read operations do not require another Address Pointer set cycle.
SMBus Definitions
The following are definitions for some general SMBus terms: Start Condition: This condition occurs when the SDA line transitions from high to low while SCL is high. The master device uses this condition to indicate that a data transfer is about to begin. Stop Condition: This condition occurs when the SDA line transitions from low to high while SCL is high. The master device uses this condition to signal the end of a data transfer. Acknowledge and Not Acknowledge: When data are transferred to the slave device it sends an "acknowledge" (ACK) after receiving each byte. The receiving device sends an ACK by pulling SDA low for one clock. Following the last byte, a master device sends a "not acknowledge" (NACK) followed by a stop condition. A NACK is indicated by forcing SDA high during the clock after the last byte.
Writing to Registers
All writes must start with a pointer set as described previously, even if the pointer is already pointing to the desired register. The sequence is described in Figure 2. Immediately following the pointer set, the master must begin transmitting the data to be written. After transmitting each byte of data, the master must release the SDA line for one clock to allow the aSC7512 to acknowledge receiving the byte. The write operation should be terminated by a stop condition from the master.
Reading from Registers
To read from a register other than the one currently being pointed to by the address pointer register, a pointer set sequence to the desired register must be done as described previously. Immediately following the pointer
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aSC7512
set, the master must perform a repeat start condition that indicates to the aSC7512 that a read is about to occur. It is important to note that if the repeat start condition does not occur, the aSC7512 will assume that a write is taking place, and the selected register will be overwritten by the upcoming data on the data bus. The read sequence is described in Figure 4. After the start condition, the master must again send the device address and read/write bit. This time the R/ W bit must be set to 1 to indicate a read. The rest of the read cycle is the same as described in the previous paragraph for reading from a preset pointer location. If the pointer is already pointing to the desired register, the master can read from that register by setting the R/ W bit (following the slave address) to a 1. After sending an ACK, the aSC7512 will begin transmitting data during the following clock cycle. After receiving the 8 data bits, the master device should respond with a NACK followed by a stop condition. If the master is reset while the aSC7512 is in the process of being read, the master should perform an SMBus reset. This is done by holding the data or clock low for more than 35ms, allowing all SMBus devices to be reset. This follows the SMBus 2.0 specification of 25-35ms. When the aSC7512 detects an SMBus reset, it will prepare to accept a new start sequence and resume communication from a known state.
1 SCL SDA S 1 0 1 1 0 0 0 R/W
9
1
9
A
A7
A6
A5
A4
A3
A2
A1
A0
A
Start
SMBus Device Address Byte (58h)
ACK from aSC7512
Register Address Byte
ACK from aSC7512
Stop By Master
Figure 2 Register Address Pointer Set
1 SCL SDA S 1 0 1 1 0 0 0 R/W
9
1
9
1
9
A
A7
A6
A5
A4
A3
A2
A1
A0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
Start
SMBus Device Address Byte (58h)
ACK from aSC7512
Register Address Byte
ACK from aSC7512
Register Data Byte
ACK from aSC7512
Stop by Master
Figure 3 Register Write
1
9
1
9
Register Address Pointer Set + (Figure 2.) without stop by Master
S
1
0
1
1
0
0
0 R/W
A
D7
D6
D5
D4
D3
D2
D1
D0
N
Re-start
SMBus Device Address Byte (58h)
ACK from aSC7512
Register Data Byte
NACK from Master
Stop by Master
Figure 4 Register Read
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aSC7512
1 SCL SDA S 1 0 1 1 0 0 0 R/W A D7 D6 D5 D4 D3 D2 D1 D0 N Stop by Master 9 1 9
Start
SMBus Device Address Byte (58h)
ACK from aSC7512
Register Data Byte
NACK from Master
Figure 5 Register Read When Read Address Already Set
1 SCL SDA S 0 0 0 1 1 0 0 R/W A 1 0 1 1 0 0 0 1 N NACK from Master Stop by Master 9 1 9
Start
SMBus Alert Response Address Byte (0Ch)
ACK from aSC7512
aSC7512 SMBus Address
Figure 6 SMBus Alert Response
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aSC7512
Operation
ALERT Output
The ALERT pin will remain low until the status bits have been reset and an Alert Response has been issued by the master and responded by the aSC7512. This flow is described below. The user may mask-out or disable the ALERT signal pin should it be necessary to prevent a processor interrupt. This is controlled by setting bit 7 of the configuration register.
The aSC7512 has an emergency alarm function,
ALERT that is optionally assigned to pin 6, the TACH / ALERT pin. ALERT is determined by both high and low limits and will also respond to a remote diode open circuit failure. These limits are settable separately for Zone 1 and Zone 2 sensors. Any alarm condition is reported individually in the status register and may be read at any time on the SMBus. Alarm conditions are logically combined and used to drive an open-drain output, the ALERT output, (pin 6).
SMBus Alert Output
The ALERT pin may be used to signal an SMBus Alert to the host processor. This is a special mode of the SMBus interface that requires the SMBus host to send an Alert Response Address (ARA) to all slaves sharing the
ALERT pin in order to isolate clear and service the alerting device. This sequence is described below and in Figure 6.
This output pin may be used as an interrupt signal the CPU or to turn on remote drivers for fans or indicators. The ALERT pin will remain asserted until it has been reset by the host via the SMBus.
The sequence of servicing this interrupt is as follows: 1. 2.
ALERT is asserted by the aSC7512 driving pin 6 low.
ALERT Limits
Figure 7 shows use of the ALERT high and low limits. The user sets up the alarm by writing the upper and lower limit temperatures into the limit registers over the SMBus. After each measurement, the comparator tests the readings against the programmed limits and if the measurement exceeds the high limit is or is equal to or less-than the low limit, it will assert the particular alarm bits in the status register and cause the ALERT pin to go low.
Conversion ZN1 High ALERT Limit Temperature ZN1 Low ALERT Limit Status Bit-4, RHIGH Status Bit-3, RLOW Status Register Read
ALERT Pin 6
The SMBus master begins a read operation with a start followed by the ARA response address, 0001 100. This is an SMBus General Call Address to be used only for requesting an alert response. The device providing the ALERT signal responds to this by providing an ACK followed by its own bus address, an aSC7512 will provide, 101 1000, with the LSB of the data byte set to 1. A NACK response is expected from all devices not giving an ALERT . If more than one device responds, the device with the lowest device address will have priority and will be serviced first by the master. The service routine must read the status register of the alerting device to determine the nature of the alert. If the alerting condition is still present, the status bit will remain set, continuing to activate the ALERT pin. If the condition is removed, the status bit will be cleared and an additional ARA will now de-assert the
ALERT pin.
3.
4.
5.
ARA Response
Figure 7 ALERT Limits and Responses
The status bits will remain high until the status register is read and then, if the condition is no longer present those bits will be reset, otherwise they will remain high until the conditions are no longer met and the register is read again. The same sequence applies to the local readings and limits.
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aSC7512
Register Set
Register Address Register Name
Alert Status Configuration Conversion Rate Zone 2 High Alert Limit Zone 2 Low Alert Limit Zone 1 High Alert Limit (MS byte) Zone 1 Low Alert Limit (MS byte) One shot Measurement Zone 1 Temperature (LS Byte) Zone 1 Offset (MS byte) Zone 1 Offset (LS byte) Zone 1 High Alert Limit (LS byte) Zone 1 Low Alert Limit (LS byte) Zone 2 Temperature (LS Byte) Consecutive Alert Zone 1 Temperature Zone 2 Temperature Tach LSB Tach MSB Fan Current PWM Duty Tach Configuration Company ID Version/ Stepping Ready/Lock/ Start/Override
R/W
R R/W R/W R/W R/W R/W
Bit 7 (MSB)
BUSY Alert Mask
CONV7
Bit 6
LHIGH Run/ Stop
CONV6
Bit 5
LLOW Alert/ Tach
CONV5
Bit 4
RHIGH RES
CONV4
Bit 3
RLOW RES
CONV3
Bit 2
ROPEN RES
CONV2
Bit 1
X RES
CONV1
Bit 0 (LSB)
X RES
CONV0
Default Value (hex)
00 00 08 55 00 55
02h 09h 0Ah 0Bh 0Ch 0Dh
7 7 9
6 6 8
5 5 7
4 4 6
3 3 5
2 2 4
1 1 3
0 0 2
0Eh 0Fh 10h 11h 12h 13h
R/W R/W R R/W R/W R/W
9 RES 1 9 1 1
8 RES 0 8 0 0
7 RES X 7 RES X
6 RES X 6 RES X
5 RES X 5 RES X
4 RES X 4 RES X
3 RES X 3 RES X
2 RES X 2 RES X
00 00 00 00 00 00
14h
R/W
1
0
X
X
X
X
X
X
00
15h
R
1 SMB Timeout 9 9 7 15 7
Tach1 Disable
0
X
X
X Consec Alert 3 5 5 3 11 3
Meas Dwell 1
X Consec Alert 2 4 4 2 10 2
Meas Dwell 0
X Consec Alert 1 3 3 1 9 1
Meas Duration 1
X Consec Alert 0 2 2 0 8 0
Meas Duration 0
00
22h 25h 26h 28h 29h 30h 3Ah 3Eh 3Fh 40h
R/W R R R R R/W R/W R R R/W
RES 8 8 6 14 6
3-Wire Enable
RES 7 7 5 13 5
Meas Blank1
RES 6 6 4 12 4
Meas Blank 0
01 00 00 00 00 FF 36 61 62 00
7 VER3 RES
6 VER2 RES
5 VER1 RES
4 VER0 RES
3 STP3 OVRID
2 STP2 READY
1 STP1 LOCK
0 STP0 START
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Lock
aSC7512
Register Address R/W Register Name
Interrupt Status Register 1 Interrupt Status Register 2 Zone 1 Low Temperature Zone 1 High Temperature Zone 2 Low Temperature Zone 2 High Temperature Tach Minimum LSB Tach Minimum MSB Fan Configuration Fan Range/ Frequency Zone 2 Range Min/Off, Zone1 Spike Smoothing Zone2 Spike Smoothing Fan PWM Minimum Zone1 Fan Temp Limit Zone 2 Fan Temp Limit Zone 1 Temp Absolute Limit Zone 2 Temp Absolute Limit Zone 1, Zone 2 Hysteresis Fan Spin-up Mode
Bit 7 (MSB)
ERR RES 7 7 7 7 7 15 ZON2 RAN3 RAN3 RES ZN2E 7 7 7 7 7 H1-3 RES
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RES RES 0 0 0 0 0 8 SPIN0 FRQ0 RES ZN1-0 RES 0 0 0 0 0 H2-0 PWM1SU
Default Value (hex)
00 00 81 7F 81 7F FF FF 62 C3 C3 00 00 80 5A 5A 64 64 44 07
41h 42h 4Eh 4Fh 50h 51h 54h 55h 5Ch 5Fh 60h 62h 63h 64h 67h 68h 6Ah 6Bh 6Dh 75h
R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
RES ERR1 6 6 6 6 6 14 ZON1 RAN2 RAN2 RES ZN2-2 6 6 6 6 6 H1-2 RES
ZN2 RES 5 5 5 5 5 13 ZON0 RAN1 RAN1 OFF1 ZN2-1 5 5 5 5 5 H1-1 RES
ZN1 RES 4 4 4 4 4 12 INV RAN0 RAN0 RES ZN2-0 4 4 4 4 4 H1-0 RES
RES RES 3 3 3 3 3 11 RES HLFRQ RES ZN1E RES 3 3 3 3 3 H2-3 RES
RES FAN 2 2 2 2 2 10 SPIN2 FRQ2 RES ZN1-2 RES 2 2 2 2 2 H2-2 RES
RES RES 1 1 1 1 1 9 SPIN1 FRQ1 RES ZN1-1 RES 1 1 1 1 1 H2-1 RES
Note: Reserved bits will always return 0 when read, X-bits in readings are to be ignored.
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Lock
X X X X X X X X X X X X X X
aSC7512
Temperature Measurement
Temperatures are measured with a precision Delta-VBE methodology converted to a digital temperature reading by a 10-bit sigma-delta converter. The user may set limits on these readings to be continuously monitored and alarm bits set when they are exceeded. Separately, the measurements are also delivered to the automatic fan control system to adjust fan speed. The following registers contain the readings from the internal and remote sensors.
Registers 25-10h and 26-15h: Zone Temperature Reading (10-Bit, 2's Complement Reporting)
Register Address
25h 10h 26h 15h
Read/ Write
R R R R
Register Name
Zone 1 Temperature Zone 1 Temperature (LS Byte) Zone 2 Temperature Zone 2 Temperature (LS Byte)
Bit 7 (MSB)
9 1 9 1
Bit 6
8 0 8 0
Bit 5
7 X 7 X
Bit 4
6 X 6 X
Bit 3
5 X 5 X
Bit 2
4 X 4 X
Bit 1
3 X 3 X
Bit 0 (LSB)
2 X 2 X
Default Value
00 00 00 00
The Zone Temperature registers reflect the current temperature of the internal and remote diodes. Processor (Zone 1) Temp register reports the temperature measured by the thermal diode connected to the Remote - and Remote + pins. Internal (Zone 2) Temp register reports the temperature measured by the internal (junction) temperature sensor. Temperatures are represented as 10 bit, 2's complement, signed numbers, in Celsius, as shown below in Table 1. The Temperature Reading register will return a value of 8000h if the remote diode pins are not used by the board designer or are not functioning properly. This reading will cause the zone limit bit (bit 4) in the Interrupt Status Register (41h) and the remote diode fault status bit (bit 6) in the Interrupt Status Register 2 (42h) to be set. These registers are read-only - a write to these registers has no effect.
Digital Output (2's Complement) Temperature +125C +100C +50C +25C +10C +1.75C +0.25C 0C -1.75C -55C
High Byte 10-Bit Resolution Low Byte
Ignore XX XX XX XX XX XX XX XX XX XX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0111 0110 0011 0001 0000 0000 0000 0000 1111 1100
1101 0100 0010 1001 1010 0001 0000 0000 1110 1001
00 00 00 00 00 11 01 00 01 00
Table 1 Relationship between Temperature and 2's Complement Digital Output, -55C to +125C
Temperature Measurement Configuration and ALERT Limits
Registers 09h, 0Ah, 0Fh, 22h: Conversion Rate and ALERT Configuration
Register Address
09h 0Ah
Read/ Write
R/W R/W
Register Name
Configuration Conversion Rate
Bit 7 (MSB)
Alert Mask
CONV7
Bit 6
Run/ Stop
CONV6
Bit 5
Alert/ Tach
CONV5
Bit 4
RES
CONV4
Bit 3
RES
CONV3
Bit 2
RES
CONV2
Bit 1
RES
CONV1
Bit 0 (LSB)
RES
CONV0
Default Value
00 08
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aSC7512
Register Address
0Fh 22h
Read/ Write
R/W R/W
Register Name
One shot Measurement Consecutive Alert
Bit 7 (MSB)
RES SMB Timeout
Bit 6
RES RES
Bit 5
RES RES
Bit 4
RES RES
Bit 3
RES Consec Alert 3
Bit 2
RES Consec Alert 2
Bit 1
RES Consec Alert 1
Bit 0 (LSB)
RES Consec Alert 0
Default Value
00 01
These configuration register settings apply to measurements and alerts reported in registers 25h-10h and 26h-15h temperature readings (10-Bit 2's complement reporting). One-shot Measurement register address 0Fh initiates a temperature measurement when aSC7512 is in Stop mode and returns to that mode after both temperature measurements are complete.
Bit
0:3 5 6 7
Name
Reserved Alert/Tach Run/Stop Alert Mask
R/W
R/W R/W R/W R/W
Default
0 0 0 0 Reserved
Description
Selection between Tach input and ALERT output for pin 6, default is Tach input. Measurement system run(default) or stop, places aSC7512 in a low-power or standby mode. Mask alarm conditions from asserting ALERT pin 6 when ALERT function of pin 6 is enabled.
Table 2 Configuration Register [09h] bits
Bit
Name
R/W
Default
Description
Temperature measurement rate for a set of internal and external readings. Conversions per Second 0.0625 0.125 0.25 0.5 1 2 4 5 8 16 (default) 32 64 Seconds per Conversion 16 8 4 2 1 0.5 0.25 0.2 0.125 0.0625 0.03125 0.015625
Code (Hex) 00 01 02 03 04 05 06 D0 07 08 09 0A
3:0
Conversion Rate
R/W
08h
Table 3 Conversion Rate Register [0Ah] bits
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aSC7512
Bit
Name
R/W
Default
Description
The number of consecutive out-of-limit measurements required to set the ALERT pin.
3:0
Consecutive Alert
R/W
000
1: 000 2: 001 3: 011 4: 111
6 7
Reserved SMBTimeout
R/W R/W
0 0
Reserved Enables a reset of the aSC7512 SMBus interface if it detects SMBus clock stuck low for more than 35 milliseconds.
Table 4 Consecutive Alert Register [22h] bits Register 0B-0Eh and 11-14h: ALERT Temperature Limits (Compared to Registers 25h-14h, 26h-15h)
Register Address
0Bh 0Ch 0Dh 13h 0Eh 14h
Read/ Write
R/W R/W R/W R/W R/W R/W
Register Name
Zone 2 High Alert Limit Zone 2 Low Alert Limit Zone 1 High Alert Limit (MS byte) Zone 1 High Alert Limit (LS byte) Zone 1 Low Alert Limit (MS byte) Zone 1 Low Alert Limit (LS byte)
Bit 7 (MSB)
7 7 9 1 9 1
Bit 6
6 6 8 0 8 0
Bit 5
5 5 7 X 7 X
Bit 4
4 4 6 X 6 X
Bit 3
3 3 5 X 5 X
Bit 2
2 2 4 X 4 X
Bit 1
1 1 3 X 3 X
Bit 0 (LSB)
0 0 2 X 2 X
Default Value
55 00 55 00 55 00
These limits are compared Zone 1 and Zone 2 registers and trigger the optional ALERT signal pin and status bits that may be enabled in Register 09h, Bit-5. The limits are in binary temperature format representing values from 0 to +127 degrees.
Status Registers
Register 02h: Alert Status Register
Register Address
02h
Read/ Write
R
Register Name
Alert Status
Bit 7 (MSB)
BUSY
Bit 6
LHIGH
Bit 5
LLOW
Bit 4
RHIGH
Bit 3
RLOW
Bit 2
ROPEN
Bit 1
RES
Bit 0 (LSB)
RES
Default Value
00
The Alert Status Register is a read-only register for reporting the state of the aSC7512's alarms. It is a read-only register located at 02h. When any high or low Zone 1 (remote) limits or high or low Zone 2 (local) limits are exceeded, bits 3 through 6 are set accordingly and the ALERT pin 6 will be driven low. If the remote sensor is open-circuit, bit 2 will be set and the ALERT will be asserted. Reading the status register will re-set these flags if the alerted condition has been removed, however, the ALERT pin will remain asserted until the master has serviced the SMBus alert. This register is read-only - a write to this register has no effect.
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aSC7512
Bit
1:0 2 3 4 5 6 7
Name
RESERVED ROPEN RLOW RHIGH LLOW LHIGH BUSY
R/W
R R R R R R R
Default
0 0 0 0 0 0 0 RESERVED
Description
ZONE 1 (REMOTE) SENSOR OPEN-CIRCUIT ZONE 1 (REMOTE) SENSOR LOW LIMIT ZONE 1 (REMOTE) SENSOR > HIGH LIMIT ZONE 2 (LOCAL) SENSOR LOW LIMIT ZONE 2 (LOCAL) SENSOR > HIGH LIMIT CONVERTER IN PROCESS OF CONVERSION
Table 5 Alert Status Register Register 41h: Interrupt Status Register 1
Register Address
41h
Read/ Write
R
Register Name
Interrupt Status 1
Bit 7 (MSB)
ERR
Bit 6
RES
Bit 5
ZN2
Bit 4
ZN1
Bit 3
RES
Bit 2
RES
Bit 1
RES
Bit 0 (LSB)
RES
Default Value
00
The Interrupt Status Register 1 bits will be automatically set, by the aSC7512, whenever a fault condition is detected. A fault condition is detected whenever a measured value is outside the window set by its limit registers. ZN1 bit will be set when a diode fault condition, such as an open or short, is detected. More than one fault may be indicated in the interrupt register when read. The register will hold a set bit(s) until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the aSC7512 after it is read by software, if the fault condition no longer exists. Once set, the Interrupt Status Register 1 bits will remain set until a read event occurs, even if the fault condition no longer exists. This register is read-only - a write to this register has no effect.
Bit
3:0
Name
RES Zone 1 Limit Exceeded
R/W
R
Default
0 Reserved
Description
The aSC7512 automatically sets this bit to 1 when the temperature input measured by the Remote1- and Remote1+ inputs is less than or equal to the limit set in the Processor (Zone 1) Low Temp register or more than the limit set in the Processor (Zone 1) High Temp register. This bit will be set when a diode fault is detected. The aSC7512 automatically sets this bit to 1 when the temperature input measured by the internal temperature sensor is less than or equal to the limit set in the thermal (Zone2) Low Temp register or greater than the limit set in the Internal (Zone2) High Temp register. Reserved If there is a set bit in Status Register 2, this bit will be set to 1.
4
R
0
5 6 7
Zone 2 Limit Exceeded RES Error in Status Register 2
R R R
0 0 0
Table 6 Interrupt Status Register 1 Register 42h: Interrupt Status Register 2
Register Address
42h
Read/ Write
R
Register Name
Bit 7 (MSB)
RES
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
RES
Default Value
00
Interrupt Status 2
ERR1
RES
RES
RES
FAN
RES
The Interrupt Status Register 2 bits will be automatically set, by the aSC7512, whenever a fault condition is detected. Interrupt Status Register 2 identifies faults caused by temperature sensor error, fan speed dropping below minimum set by the tachometer minimum register. Interrupt Status Register 2 will hold a set bit until the event is read by software. The contents of this register will be cleared (set to 0) automatically by the aSC7512 after it is read by software, if fault condition no longer exists. Once set, the Interrupt Status Register 2 bits will remain set until a read event occurs, even if the fault no longer exists. This register is read-only - a write to this register has no effect.
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aSC7512
Bit
0:1 2 5:3 6 7
Name
RES FAN STALLED RES Remote Diode Fault RES
R/W
R R R R R
Default
0 0 0 0 0 Reserved
Description
The aSC7512 automatically sets this bit to 1 when the TACH1 input reading is above the count value set in the Tach1 Minimum MSB and LSB registers. Reserved The aSC7512 automatically sets this bit to 1 when there is an open circuit fault on the Remote1+ or Remote1- thermal diode input pins. A diode fault will also set bit 4 Diode 1 Zone Limit bit, of Interrupt Status Register 1. Reserved
Table 7 Interrupt Status Register 2
Tachometer Measurement and Configuration
Register 28-29h: Fan Tachometer Reading
Register Address
28h 29h
Read/ Write
R R
Register Name
Tach LSB Tach MSB
Bit 7 (MSB)
7 15
Bit 6
6 14
Bit 5
5 13
Bit 4
4 12
Bit 3
3 11
Bit 2
2 10
Bit 1
1 9
Bit 0 (LSB)
0 8
Default Value
N/A N/A
The Fan Tachometer Reading registers contains the number of 11.111s periods (90 kHz) between full fan revolutions. The results are based on the time interval of two tachometer pulses, since most fans produce two tachometer pulses per full revolution. These registers will be updated at least once every second. The value, for each fan, is represented by a 16-bit unsigned number. The Fan Tachometer Reading registers will always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, however, if PWM command (register 30h) is zero, tach measurements are suspended and the last reading may remain in the register. FF FFh indicates that the fan is not spinning, or that the tachometer input is not connected to a valid signal. These registers are read-only - a write to these registers has no effect. When the LSByte of the aSC7512 16-bit register is read, the other byte (MSByte) is latched at the current value until it is read. At the end of the MSByte read the Fan Tachometer Reading registers are updated. During spin-up, the PWM duty cycle reported is 0%.
Register 3Ah: Fan Tachometer Measurement Configuration
Register Address
3Ah
Read/ Write
R/W
Register Name
Tach1 Configuration
Bit 7 (MSB)
Tach1 Disable
Bit 6
3-Wire Enable
Bit 5
Meas Blank 1
Bit 4
Meas Blank 0
Bit 3
Meas Dwell 1
Bit 2
Meas Dwell 0
Bit 1
Meas Duration 1
Bit 0 (LSB)
Meas Duration 0
Default Value
36
The Fan Tachometer Configuration registers contain the settings that define the modes of measurement of the Tachometer input signal. The user is allowed to disable a tachometer measurement or to request PWM stretching, in the case of a 3-wire fan. Also, the rate, start-up and period of measurements within a fan rotation cycle may be selected. The table below describes the controls.
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aSC7512
Bit
Name
R/W
Default
Description
The amount of fan rotation used for the tach measurement. Assumes 2 pulse periods per rotation of fan.
1:0
Measurement Duration
R/W
10
00: 1/4 Rotation - Tach Count x4 = Reported Value 01: 1/2 Rotation - Tach Count x2 = Reported Value 10: 1 Rotation - Tach Count x1 = Reported Value (default) 11: 2 Rotation - Tach Count x1 = Reported Value Delay between Tach Measurements 00: 100 ms
3:2
Measurement Dwell
R/W
01
01: 300 ms (default) 10: 500 ms 11: 728 ms In 3-wire fan mode, a delay is needed to assure that the tach input has stabilized after the PWM has been set to 100%
5:4
Measurement Blank
R/W
11
00: 11.1 s 01: 22.2 s 10: 33.3 s 11: 44.4 s (default) When high, forces the PWM to stay high for the duration of a tach measurement for a 3-wire fan. This will result in increasing the PWM on-time percentage vs. the value in the PWM register. Suspends the 90KHz clock for power savings when high.
6 7
3-Wire Enable Tach Disable
R/W R/W
0 0
Table 8 Tachometer Configuration Register
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aSC7512
Automatic Fan Control
Auto Fan Control Operating Mode
The aSC7512 includes the circuitry for automatic fan control. In Auto Fan Mode, the aSC7512 will automatically adjust the PWM duty cycle of the PWM output. PWM outputs are assigned to a thermal zone based on the fan configuration registers. At any time, the temperature of a zone exceeds its absolute limit, all PWM outputs will go to 100% duty cycle to provide maximum cooling to the system.
Fan Temp Limit less Hysteresis Fan Temp Limit Fan Temp Limit plus Range Absolute Limit
Hysteresis (0 C to 15 C)
Range (2 C to 80 C)
rly linea ycle mp C arly line Duty h Te WM sing wit ty Cycle h Temp P t u ea g wi MD Incr PW creasin De
100%
PWM Set to Minimum
PWM %
User Choice: Set to Minimum or Off PWM Set to Off
0% Temperature
PWM set to Off or Minimum Below this Temperature
Linear Control Range
PWM 100%
Example
Temperature C
5 C Hysteresis 45 50
8 C Range 58 80
Off/ Min% 100% Min% Minimum PWM set to 50%, fan speed increases linearly beyond 50 C but will not return to off until it has gone below Fan Temp Limit by the 5 C Hysteresis setting to 45C. PWM %
Figure 8 Automatic Fan Speed Control Example
Example for PWM1 assigned to Zone 1: * * * Zone 1 Fan Temp Limit (Register 67h) is set to 50C (32h). Zone 1 Range (Register 5Fh) is set to 8C (6xh). Fan PWM Minimum (Register 64h) is set to 50% (32h).
In this case, the PWM duty cycle will be 50% at 50C. Since (Zone 1 Fan Temp Limit) + (Zone 1 Range) = 50C + 8C = 58C, the fan will run at 100% duty cycle when the temperature of the Zone 1 sensor reaches 58C. Since the midpoint of the fan control range is 54C, and the median duty cycle is 75% (Halfway between the PWM Minimum and 100%), PWM1 duty cycle would be 75% at 54C. Above (Zone 1 Fan Temp Limit) + (Zone 1 Range), the duty cycle will be 100%.
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aSC7512
Auto Fan Mode Initiated End Polling Cycle No Min Speed or Spin-Up Time Met? End Fan Spin Up Begin Polling Cycle
Yes
Yes
Fan Spinning Up? No
Set Fan Output to 0%
Set fan output to auto fan mode minimum speed
Override PWM Output to 100%
Yes
Temp >= AbsLimit? No Temp >= Limit? Yes No Off / Min set to 1? No (off) No Temp >= Hysteresis? Yes
Yes (Minimum Speed)
Set Fan Output to 100%
Begin Fan Spin up
Yes
Fan Output at 0%? No Set fan speed based on Auto Fan Range Algorithm
Fan Output At 0%? Yes
No
Figure 9 Automatic Fan Control Algorithm Fan Register Device Set-Up
The BIOS will follow the following steps to configure the fan registers on the aSC7512. The registers corresponding to each function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by the BIOS to the fan limit and parameter registers during configuration, the aSC7512 will continue to operate based on default values until the START bit (bit 0), in the Ready/Lock/Start/Override register (address 40h), is set. Once the fan mode is updated, by setting the START bit to 1, the aSC7512 will operate using the values that were set by the BIOS in the fan control limit and parameter registers (address in the range 5Ch through 6Dh). 1. Set limits and parameters (not necessarily in this order): * * * * * * * * * 2. [5F-60h] Set PWM frequency for the fan and auto fan control range for each zone. [62-63h] Set spike smoothing and min/off. [5Ch] Set the fan spin-up delay. [75h] Set PWM spin-up mode to terminate after time set in [5Ch]. Value = 00h instead of default 01h. [5Ch] Match fan with a corresponding thermal zone. [67-68h] Set the fan temperature limits. [6A-6Bh] Set the temperature absolute limits. [64h] Set the PWM minimum duty cycle. [6Dh] Set the temperature hysteresis values.
[40h] Set bit 0 (START) to update fan control and limit register values and start fan control based on these new values.
[40h] (Optional) Set bit 1 (LOCK) to lock the fan limit and parameter registers. WARNING: this is a non-reversible change in state and locks out further change in critical fan control parameters until power is removed from the aSC7512.
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aSC7512
Register 5F-60h: Auto Fan Speed Range, PWM Frequency
Register Address
5Fh 60h
Read/ Write
R/W R/W
Register Name
Zone 1 Range Fan1 Frequency Zone 2 Range
Bit 7 (MSB)
RAN3 RAN3
Bit 6
RAN2 RAN2
Bit 5
RAN1 RAN1
Bit 4
RAN0 RAN0
Bit 3
HLFRQ RES
Bit 2
FRQ2 RES
Bit 1
FRQ1 RES
Bit 0 (LSB)
FRQ0 RES
Default Value
C3 C3
Lock
X X
In Auto Fan Mode, when the temperature for a zone is above the Temperature Limit (Registers 67-69h) and below its Absolute Temperature Limit (Registers 6A-6Bh), the speed of a fan assigned to that zone is determined as follows: When the temperature reaches the Fan Temp Limit for a zone, the PWM output assigned to that zone will be Fan PWM Minimum. Between Fan Temp Limit and (Fan Temp Limit + Range), the PWM duty cycle will increase linearly according to the temperature as shown in the figure below. The PWM duty cycle will be 100% at (Fan Temp Limit + Range). PWM frequency - FRQ[3:0] and HLFRQ The PWM frequency bits [3:0] determine the PWM frequency for the fan. The aSC7512 has high and low frequency ranges for the PWM outputs that are controlled by the HLFRQ bit. PWM Frequency Selection (Default = 0011 = 30.04 Hz).
HLFRQ
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FRQ [2:0]
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
PWM Frequency
10.01 Hz 15.02 Hz 23.14 Hz 30.04 Hz (Default) 38.16 Hz 47.06 Hz 61.38 Hz 94.12 Hz 22.5 kHz 24 kHz 25.7 kHz 25.7 kHz 27.7 kHz 27.7 kHz 30 kHz 30 kHz
Table 9 Register Setting vs PWM Frequency
RAN[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 (c) Andigilog, Inc. 2006
Linear Control Range (C)
2 2.5 3.33 4 5 6.67 8 10 13.33 16
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aSC7512
RAN[3:0]
1010 1011 1100 1101 1110 1111
Linear Control Range (C)
20 26.67 32 (default) 40 53.33 80
Table 10 Zone Range Setting, RAN[3:0]
This register becomes Read-Only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
Register 40h: Ready/Lock/Start/Override
Register Address
40h
Read/ Write
R/W
Register Name
Ready/Lock/Start/ Override
Bit 7 (MSB)
RES
Bit 6
RES
Bit 5
RES
Bit 4
RES
Bit 3
OVRID
Bit 2
READY
Bit 1
LOCK
Bit 0 (LSB)
START
Default Value
00
Bit
Name
R/W
Default
Description
When software writes a 1 to this bit, the aSC7512 fan monitoring and PWM output control functions will use the values set in the fan control limit and parameter registers (address 5Ch through 6Eh). Before this bit is set, the aSC7512 will not update the used register values, the default values will remain in effect. Whenever this bit is set to 0, the aSC7512 fan monitoring and PWM output control functions use the default fan limits and parameters, regardless of the current values in the limit and parameter registers (5C through 6E). The aSC7512 will preserve the values currently stored in the limit and parameter registers when this bit set or cleared. This bit is not affected by the state of the Lock bit. It is expected that all limit and parameter registers will be set by BIOS or application software prior to setting this bit.
0
START
R/W
0
1
LOCK
R/W
0
Setting this bit to 1 locks specified limit and parameter registers. WARNING: Once this bit is set, limit and parameter registers become read-only and will remain locked until the device is powered off. This register bit becomes read-only once it is set. The aSC7512 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all A/D converters are properly functioning. If this bit is set to 1, all PWM outputs will go to 100% duty cycle regardless of whether or not the lock bit is set. The OVRID bit has precedence over the disabled mode. Therefore, when OVRID is set the PWM will go to 100% even if the PWM is in the disabled mode. Reserved
2
READY
R
0
3 4-7
OVRID RESERVED
R/W R
0 0
Table 11 READY / LOCK / START / OVRID Settings
Register 30h: Current PWM Duty Cycle
Register Address
30h
Read/ Write
R/W
Register Name
Fan Current PWM Duty
Bit 7 (MSB)
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0 (LSB)
0
Default Value
N/A
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aSC7512
The Current PWM Duty registers store the current duty cycle at each PWM output. At initial power-on, the PWM duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start/Override register Start bit is set, this register and the PWM signals will be updated based on the algorithm described in the Auto Fan Control Operating Mode section. When read, the Current PWM Duty registers return the current PWM duty cycle. These registers are read-only unless the fan is in manual (test) mode, in which case a write to these registers will directly control the PWM duty cycle for each fan. The PWM duty cycle is represented as shown in Table 12. If a 3-wire fan is being used and the option to enable 3-wire tach measurement is selected, the effective PWM duty cycle will be impacted by this feature. The 3-wire Enable setting will hold the PWM signal high for the period taken to make a tachometer reading. This period depends on the RPM and various tachometer measurement parameters. Overall impact is that lower PWM commands will be effectively increased and there may be acoustic effects. Current PWM % 0% ~25% ~50% (Default) ~75% 100% Register Value Binary 0000 0100 1000 1100 1111 0000 0000 0000 0000 1111 Hex 00 40 80 C0 FF
Table 12 Current PWM Duty Cycle Setting Register 4E-51h: Thermal Zone Temperature Limit Registers
Register Address
4Eh 4Fh 50h 51h
Read/ Write
R/W R/W R/W R/W
Register Name
Zone 1 Low Temp Zone 1 High Temp Zone 2 Low Temp Zone 2 High Temp
Bit 7 (MSB)
7 7 7 7
Bit 6
6 6 6 6
Bit 5
5 5 5 5
Bit 4
4 4 4 4
Bit 3
3 3 3 3
Bit 2
2 2 2 2
Bit 1
1 1 1 1
Bit 0 (LSB)
0 0 0 0
Default Value
81 7F 81 7F
If an external temperature input or the internal temperature sensor either exceeds the value set in the corresponding high limit register or falls below the value set in the corresponding low limit register, the corresponding bit will be set automatically by the aSC7512 in the Interrupt Status Register 1 (41h). For example, if the temperature read from the Remote - and Remote + inputs exceeds the Zone 1 High Temp register limit setting, Interrupt Status Register 1 ZN1 bit will be set. The temperature limits in these registers are represented as 8 bit 2's complement, signed numbers in Celsius, as shown below in Table 13. Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers. Temperature Limit (2's Complement) 0111 0111 0111 0101 0011 0001 0000 1100 1000 1111 1111 1101 1010 0010 1001 0000 1110 0001
Temperature >127C +127C (Default High) +125C +90C +50C +25C 0C -50C -127C (Default Low)
Table 13 Zone Temperature High- and Low-Limit Registers - 8-Bit Two's Complement
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aSC7512
Register 54-55h: Fan Tachometer Minimum Limits
Register Address
54h 55h
Read/ Write
R/W
Register Name
Tach Minimum LSB Tach Minimum MSB
Bit 7 (MSB)
7 15
Bit 6
6 14
Bit 5
5 13
Bit 4
4 12
Bit 3
3 11
Bit 2
2 10
Bit 1
1 9
Bit 0 (LSB)
0 8
Default Value
FF FF
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at low speeds, so care should be taken in software to ensure that the limit is high enough not to cause sporadic alerts. The fan tachometer will not cause a bit to be set in Interrupt Status Register 2 if the current value in Current PWM Duty registers is 00h or if the fan 1 disabled via the Fan Configuration Register. Interrupts will never be generated for a fan if its minimum is set to FF FFh. Given the relative insignificance of Bit 0 and Bit 1 of Tach Minimum LSB, these bits could be programmed to designate the physical location of the fan generating the tachometer signal, as follows: Register Name
CPU Cooler Memory Controller Chassis Front Chassis Rear
Bit 1
0 0 1 1
Bit 0 (LSB)
0 1 0 1
Table 14 Fan Location
Setting the Ready/Lock/Start/Override register Lock bit has no effect on these registers.
Register 5Ch: Fan Thermal Zone Assignment and Spin-up Mode
Register Address
5Ch
Read/ Write
R/W
Register Name
Fan Configuration
Bit 7 (MSB)
ZON2
Bit 6
ZON1
Bit 5
ZON0
Bit 4
INV
Bit 3
RES
Bit 2
SPIN2
Bit 1
SPIN1
Bit 0 (LSB)
SPIN0
Default Value
62
Lock
X
This register becomes Read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible. Bits [7:5] Zone/Mode Bits [7:5] of the Fan Configuration registers associate each fan with a temperature sensor. When in Auto Fan Mode the fan will be assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of that zone. If "Hottest" option is selected (110), the fan will be controlled by the the hotter of zones 1, or 2. To determine the "hotter zone", the PWM level for each zone is calculated then the zone with the higher PWM value (not temperature) is selected. When in manual control mode, the Current PWM duty register (30h) become Read/Write. It is then possible to control the PWM outputs with software by writing to these registers. When the fan is disabled (100) the corresponding PWM output should be driven low (or high, if inverted). Zone 1: External Diode (processor) Zone 2: Internal Sensor
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aSC7512
Fan Configuration
Fan on Zone 1 auto Fan on Zone 2 auto Reserved Fan always on full Fan disabled Fan on Zone 2 auto Fan controlled by hotter of zones 1 or 2 Fan manually controlled (Test Mode)
ZON[2:0]
000 001 010 011 100 101 110 111
Table 15 Fan Zone Setting
Bit [4] PWM Invert Bit [4] inverts the PWM output. If set to 0, 100% duty cycle will yield an output that is always high. If set to 1, 100% duty cycle will yield an output that is always low. Bit [3] Reserved Bit [2:0] Spin Up Bits [2:0] specify the `spin up' time for the fan. When a fan is being started from a stationary state, the PWM output is held at 100% duty cycle for the time specified in the table below before scaling to a lower speed.
Spin Up Time
0 ms 100 ms 250 ms 400 ms 700 ms 1000 ms 2000 ms 4000 ms
SPIN[2:0]
000 001 010 011 100 101 110 111
Table 16 Fan Spin-Up Register Register 62, 63h: Min/Off, Spike Smoothing
Register Address
62h 63h
Read/ Write
R/W R/W
Register Name
Min/Off, Zone1 Spike Smoothing Zone2 Spike Smoothing
Bit 7 (MSB)
RES ZN2E
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
ZN1-0 RES
Default Value
00 00
Lock
RES ZN2-2
OFF ZN2-1
RES ZN2-0
ZN1E RES
ZN1-2 RES
ZN1-1 RES
X X
The Off/Min Bit 5 specifies whether the duty cycle will be 0% or Minimum Fan Duty when the measured temperature falls below the Temperature LIMIT register setting (see Table 18 below). If the Remote pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the aSC7512. Fan speed algorithm has two phases of filtering on temperature zone readings. First, a "No-Spike" value is created from the current temperature and three previous readings. This is an average of the two remaining values when the high and low values are removed. This is the temperature used to determine PWM and is always running. The second phase is a user specified filter and coefficient. This filter determines a smoothed temperature value, Smooth Ti, by taking the No-Spike Ti, subtracting the previous smoothed temperature, Smooth Ti-1, divided by 2^N and adding that to the previously smoothed temperature. N is a user selectable coefficient, in the range 1 to 8, designated ZN1-2:ZN1-0 for Zone 1 and ZN2-2:ZN2-0 for Zone 2.
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aSC7512
For the current temperature reading Ti: No-Spike Ti = (Discard min and max of (Ti, Ti-1, Ti-2, Ti-3))/2 Smooth Ti = (No-Spike Ti - Smooth Ti-1)/2N + Smooth Ti-1 If these spikes are not filtered, the CPU fan (if connected to aSC7512) may turn on prematurely or produce unpleasant noise. For this reason, any zone that is connected to a chipset or processor should have spike smoothing enabled. Individual system characteristics will determine how large this coefficient should be. When spike smoothing is enabled, the temperature reading registers will still reflect the current value of the temperature - not the "smoothed out" value. ZN1E and ZN2E enable temperature smoothing for zones 1 and 2 respectively. ZN1-2, ZN1-1 and ZN1-0 control smoothing time for Zone 1. ZN2-2, ZN2-1 and ZN2-0 control smoothing time for Zone 2. These registers become read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect.
60 50 40 30 20 10 0 1 2 3 4 5 6 7 8 9 10 11 12
Figure 10 Representation of What Temperature Is Passed to the aSC7512 Auto Fan Control with (green) and without (red dashed) Spike Smoothing
Spike Smoothing Filter Coefficient
8 7 6 5 4 3 2 1
ZNn-[2:0]
000 001 010 011 100 101 110 111
Table 17 Spike Smoothing
PWM Action
At 0% duty below LIMIT At Min PWM Duty below LIMIT
Off/Min Bit
0 1
Table 18 PWM Output Below Limit Depending on Value of Off/Min
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aSC7512
Register 64h: Minimum PWM Duty Cycle
Register Address
64h
Read/ Write
R/W
Register Name
Fan PWM Minimum
Bit 7 (MSB)
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0 (LSB)
0
Default Value
80
Lock
X
This register specifies the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature LIMIT register setting. This register becomes Read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible. Register Value Binary 0% ~25% ~50% (Default) ~75% 100% 0000 0100 1000 1100 1111 0000 0000 0000 0000 1111 Hex 00 40 80 C0 FF
Minimum PWM %
Table 19 Minimum PWM Duty Cycle Setting Register 67-68h: Temperature Limit
Register Address
67h 68h
Read/ Write
R/W R/W
Register Name
Zone1 Fan Temp Limit Zone2 Fan Temp Limit
Bit 7 (MSB)
7 7
Bit 6
6 6
Bit 5
5 5
Bit 4
4 4
Bit 3
3 3
Bit 2
2 2
Bit 1
1 1
Bit 0 (LSB)
0 0
Default Value
5A 5A
Lock
X X
These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be turned on if it is not already. When the temperature exceeds this limit, the fan speed will be increased according to the algorithm set forth in the Auto Fan Range, PWM Frequency register description, Default = 90C = 5Ah This register becomes read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible. Temperature >127C +127C +125C +90C (default) +50C +25C 0C -50C -127C Fan Temp Limit (2's Complement) 0111 0111 0111 0101 0011 0001 0000 1100 1000 1111 1111 1101 1010 0010 1001 0000 1110 0001
Table 20 Fan Temperature Limit Register 8-Bit Two's Complement
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aSC7512
Register 6A-6Bh: Temperature Limit
Register Address
6Ah 6Bh
Read/ Write
R/W R/W
Register Name
Zone 1 Temp Absolute Limit Zone 2 Temp Absolute Limit
Bit 7 (MSB)
7 7
Bit 6
6 6
Bit 5
5 5
Bit 4
4 4
Bit 3
3 3
Bit 2
2 2
Bit 1
1 1
Bit 0 (LSB)
0 0
Default Value
64 64
Lock
X X
In the Auto Fan mode, if a zone exceeds the temperature set in the Absolute Temperature Limit register, all of the PWM outputs will increase its duty cycle to 100%. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. If set to 80h (-128C), the feature is disabled. Default = 100 C = 64h. These registers become read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect. After power up the default values are used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to these registers are possible. Temperature >127C +127C +125C +100C (default) +50C +25C 0C -50C -127C -128C (Disable) Absolute Limit (2's Complement) 0111 0111 0111 0110 0011 0001 0000 1100 1000 1000 1111 1111 1101 0100 0010 1001 0000 1110 0001 0000
Table 21 Absolute Temperature Limit Register 8-Bit Two's Complement Register 6Dh: Thermal Zone Hysteresis
Register Address
6Dh
Read/ Write
R/W
Register Name
Zone 1 and Zone 2 Hysteresis
Bit 7 (MSB)
H1-3
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
H2-0
Default Value
44
Lock
H1-2
H1-1
H1-0
H2-3
H2-2
H2-1
X
If the temperature is above Fan Temp Limit, then drops below Fan Temp Limit, the following will occur: * The fan will remain on, at Fan PWM Minimum, until the temperature goes a certain amount below Fan Temp Limit. * The Hysteresis registers control this amount. See below table for details. This register becomes read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to these registers shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible. Temperature 0C 1C 4C (default) 10C 15C Zone Hysteresis Hn-[3:0] 0000 0001 0100 1010 1111
Table 22 Zone Hysteresis Register Format
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aSC7512
Register 75h: Fan Spin-Up Mode
Register Address
75h
Read/ Write
R/W
Register Name
Fan Spin-Up Mode
Bit 7 (MSB)
RES
Bit 6
RES
Bit 5
RES
Bit 4
RES
Bit 3
RES
Bit 2
RES
Bit 1
RES
Bit 0 (LSB)
PWM SU
Default Value
07
Lock
X
The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after time programmed by the Fan Configuration register has elapsed. When set to 1, the spin-up time will terminate early if the TACH reading exceeds the Tach Minimum value or after the time programmed by the Fan Configuration register has elapsed, which ever occurs first. This register becomes Read-only when the Ready/Lock/Start/Override register Lock bit is set. Any further attempts to write to this register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
Miscellaneous Registers
Register 3Eh, FEh: Company ID
Register Address
3Eh
Read/ Write
R
Register Name
Company ID
Bit 7 (MSB)
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0 (LSB)
0
Default Value
61
The company ID register contains the company identification number. For Andigilog this is 61h. This number is assigned by Intel and is a method for uniquely identifying the part manufacturer. This register is read-only - a write to this register has no effect.
Register 3Fh: Version/Stepping
Register Address
3Fh
Read/ Write
R
Register Name
Version/Stepping
Bit 7 (MSB)
VER3
Bit 6
VER2
Bit 5
VER1
Bit 4
VER0
Bit 3
STP3
Bit 2
STP2
Bit 1
STP1
Bit 0 (LSB)
STP0
Default Value
62
The four least significant bits of the Version/Stepping register [3:0] contain the current stepping of the aSC7512 silicon. The four most significant bits [7:4] reflect the aSC7512 base device number when set to a value of 0110b. For the aSC7512, this register will read 01101000b (62h). The register is used by application software to identify which device in the hardware monitor family has been implemented in the given system. Based on this information, software can determine which registers to read from and write to. Further, application software may use the current stepping to implement work-around for bugs found in a specific silicon stepping. This register is read-only - a write to this register has no effect.
Register 70-7Fh: Vendor Specific Registers
These registers are for vendor specific features, including test registers. They will not default to a specific value on power up.
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aSC7512
Applications Information
Remote Diodes
The aSC7512 is designed to work with a variety of remote sensors in the form of the substrate thermal diode of a CPU or graphics controller or a diode-connected transistor. Actual diodes are not suited for these measurements. There is some variation in the performance of these diodes, described in terms of its departure from the ideal diode equation. This factor is called diode nonideality, nf . The equation relating diode temperature to a change in thermal diode voltage with two driving currents is: Although the temperature error caused by non-ideality difference is directly proportional to the difference from 1.008, but a small difference in non-ideality results in a relatively large difference in temperature reading. For example, if there were a 1% tolerance in the non-Ideality of a diode it would result in a 2.7 degree difference (at 0C) in the result (0.01 x 273.15). This difference varies with temperature such that a fixed offset value may only be used over a very narrow range. Typical correction method required when measuring a wide range of temperature values is to scale the temperature reading in the host firmware.
VBE
where:
KT = (nf ) ln( N ) q
Part PentiumTM III (CPUID 68h) Pentium 4, 130nM Pentium 4, 90nM Intel Pentium M AMD AthlonTM Model 6 AMD DuronTM Models 7 and 8 AMD Athlon Models 8 and 10 2N3904
nf Min
1.0057 1.001
nf Nom
1.008 1.002 1.011
nf Max
1.0125 1.003
Series Res
nf = diode non-ideality factor, (nominal 1.008). -23 K = Boltzman's constant, (1.38 x 10 ). T = diode junction temperature in Kelvins. -19 q = electron charge (1.6 x 10 Coulombs). N = ratio of the two driving currents (16).
The aSC7512 is designed and trimmed for an expected nf value of 1.008, based on the typical value for the Intel PentiumTM III and AMD AthlonTM. There is also a tolerance on the value provided. The values for other CPUs and the 2N3904 may have different nominal values and tolerances. Consult the CPU or GPU manufacturer's data sheet for the nf factor. Table 23 gives a representative sample of what one may expect in the range of non-ideality. The trend with CPUs is for a lower value with a larger spread. When thermal diode has a non-ideality factor other than 1.008 the difference in temperature reading at a particular temperature may be interpreted with the following equation: 1.008 Tactual = Treported n actual where:
3.64 3.33
1.0015 1.002 1.002 1.0000 1.003
1.0022 1.008 1.008 1.0037 1.0046
1.0029 1.016 1.016 1.0090 1.005
3.06
Table 23 Representative CPU Thermal Diode and Transistor Non-Ideality Factors CPU or ASIC Substrate Remote Diodes
A substrate diode is a parasitic PNP transistor that has its collector tied to ground through the substrate and the base (D-) and emitter (D+) brought out to pins. Connection to these pins is shown in Figure 11. The nonideality figures in Table 23 include the effects of any package resistance and represent the value seen from the CPU socket. The temperature indicated will need to be compensated for the departure from a non-ideality of 1.008. D+ CPU
Substrate
Treported = reported temperature in temperature register.
Tactual = actual remote diode temperature. nactual = selected diode's non-ideality factor, nf . Temperatures are in Kelvins or C + 273.15.
D-
aSC7512
This equation assumes that the series resistance of the remote diode is the same for each. This resistance is given in the data sheet for the CPU and may vary from 2.5 to 4.5.
Figure 11 CPU Remote Diode Connection
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aSC7512
Series Resistance
Any external series resistance in the connections from the aSC7512 to the CPU pins should be accounted for in interpreting the results of a measurement. The impact of series resistance on the measured temperature is a result of measurement currents developing offset voltages that add to the diode voltage. This is relatively constant with temperature and may be corrected with a fixed value in the offset register. To determine the temperature impact of resistance is as follows:
TR = RS x I D / TV or, TR = RS x 90A = RS x 0.391C / 230V / C
transistor's die temperature is usually not the temperature of interest and care must be taken to minimize the thermal resistance and physical distance between that temperature and the remote diode. The offset and response time will need to be characterized by the user.
Board Layout Considerations
The distance between the remote sensor and the aSC7512 should be minimized. All wiring should be defended from high frequency noise sources and a balanced differential layout maintained on D+ and D-. Any noise, both common-mode and differential, induced in the remote diode interconnect may result in an offset in the temperature reported. Circuit board layout should follow the recommendation of Figure 13. Basically, use 10-mil lines and spaces with grounds on each side of the differential pair. Choose the ground plane closest to the CPU when using the CPU's remote diode. 10 mils GND D+ 10 mils DGND
where:
TR = difference in the temperature reading from actual. RS = total series resistance of interconnect (both leads). I D = difference in the two diode current levels (90A). TV = scale of temperature vs. VBE (230V/C).
For example, a total series resistance of 10 would give an offset of +3.9C.
Figure 13 Recommended Remote Diode Circuit Board Interconnect
Noise filtering is accomplished by using a bypass capacitor placed as close as possible to the aSC7512 D+ and D- pins. A 1.0nF ceramic capacitor is recommended, but up to 3.3nF may be used. Additional filtering takes place within the aSC7512. It is recommended that the following guidelines be used to minimize noise and achieve highest accuracy: 1. Place a 0.1F bypass capacitor to digital ground as close as possible to the power pin of the aSC7512. Match the trace routing of the D+ and D- leads and use a 1.0nF filter capacitor close to the aSC7512. Use ground runs along side the pair to minimize differential coupling as in Figure 13. Place the aSC7512 as close to the CPU or GPU remote diode leads as possible to minimize noise and series resistance. Avoid running diode connections close to or in parallel with high-speed busses, staying at least 2cm away. Avoid running diode connections close to on-board switching power supply inductors. PC board leakage should be minimized by maintaining minimum trace spacing and covering traces over their full length with solder mask.
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Discrete Remote Diodes
When sensing temperatures other than the CPU or GPU substrate, an NPN or PNP transistor may be used. Most commonly used are the 2N3904 and 2N3906. These have characteristics similar to the CPU substrate diode with non-ideality around 1.0046. They are connected with base to collector shorted as shown in Figure 12. While it is important to minimize the distance to the remote diode to reduce high-frequency noise pickup, they may be located many feet away with proper shielding. Shielded, twisted-pair cable is recommended, with the shield connected only at the aSC7512 end as close as possible to the ground pin of the device. D+ 2N3906
2.
aSC7512
DD+ 3.
2N3904
aSC7512
D-
4.
Figure 12 Discrete Remote Diode Connection
As with the CPU substrate diode, the temperature reported will be subject to the same errors due to nonideality variation and series resistance. However, the
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aSC7512
*
Thermal Considerations
The temperature of the aSC7512 will be close to that of the PC board on which it is mounted. Conduction through the leads is the primary path for heat flow. The reported local sensor is very close to the circuit board temperature and typically between the board and ambient. In order to measure PC board temperature in an area of interest, such as the area around the CPU where voltage regulator components generate significant heat, a remote diode-connected transistor should be used. A surfacemount SOT-23 or SOT-223 is recommended. The small size is advantageous in minimizing response time because of its low thermal mass, but at the same time it has low surface area and a high thermal resistance to ambient air. A compromise must be achieved between minimizing thermal mass and increasing the surface area to lower the junction-to-ambient thermal resistance. In order to sense temperature of air-flows near boardmounted heat sources, such as memory modules, the sensor should be mounted above the PC board. A TO-92 packaged transistor is recommended. The power consumption of the aSC7512 is relatively low and should have little self-heating effect on the local sensor reading. At the highest measurement rate the dissipation is less than 2mW, resulting in only a few tenths of a degree rise. * * * * * *
Selectable on-board 2N3904 or wired remote diode Headers for 2-, 3- and 4-wire fans Customizable Log file of readings Saving of register setting configurations LED indicator of pin state Optional use of external 12V fan power for higher current fans Optional connection to off-board SMBus clients
Application Diagrams
The aSC7512 may be easily adapted to two-, three- or 4wire fans for precise, wider-range fan speed control when compared to variable DC drive. Pin 6 may optionally be used as ALERT , pulled up to 3.3V with a 10K resistor to warn the system of an extreme condition needing immediate attention in any fan configuration.
3.3V
5V 2-Wire Fan in Cooling Module
Remote Sensor CPU
2.2K 1 VDD D+ DPWM SMBCLK 8
2.2K
SMBCLK 2 SMBDAT TACH GND 7 SMBDAT 6
aSC7512
3 5V 10K 4 5
Optional ALERT
3.3V
Evaluation Board
The aSC7511/aSC7512EVB provides a platform for evaluation of the operational characteristics of the aSC7511 and aSC7512. The board features a graphical user interface (GUI) to control and monitor all activities and readings of the aSC7511. The provided software will run on a Windows XPTM-based desktop or laptop PC with a USB port. In addition to being a self-contained fan speed control demonstration, it may be connected into an operating PC's fan and CPU diode to evaluate various settings under real operating conditions without the need to adjust BIOS code. After optimization, the settings may be programmed into the system. Features: * Interactive GUI for setting limits and operational configuration * aSC7512 Automatic Fan Control * Powered and operated from the USB port * Graphical readouts: * Temperature and alarms * Fan RPM * Automatic fan control state
NDT3055L or FDC637AN Remote Sensor CPU 2 D+ DPWM SMBDAT TACH GND 7 SMBDAT 6 3.3V 10K 4 5 10K NDT3055L or FDC637AN Remote Sensor CPU 2 D+ DPWM SMBDAT TACH GND 7 SMBDAT 6 2.2K 1 VDD SMBCLK 8 SMBCLK 3.3V 2.2K 1 VDD SMBCLK 8 SMBCLK 2.2K
5V 3-Wire Fan in Cooling Module
aSC7512
3 5V
2.2K
12V in Cooling
4-Wire Fan Module
aSC7512
3 5V 10K 4 5
10K
15K
7.5K
Figure 14 aSC7512 2-, 3- and 4-Wire Fan Connections
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aSC7512
Physical Dimensions in millimeters unless otherwise noted:
D8 Package - 8-Lead SOP Package Dimensions Pb-Free Package
1.27mm BSC 0.53mm 7
Detail A
3.81mm (min) 3.99mm (max)
0.19mm (min) 0.25mm (max)
5.80mm (min) 6.20mm (max)
0.41mm (min) 1.27mm (max)
4.80mm (min) 4.98mm (max) 1.52mm (min) 1.72mm (max) 0.10mm (min) 0.25mm (max) 1.37mm (min) 1.57mm (max) 0.25mm (min) 0.50mm (max) x 45
Detail A
0.36mm (min) 0.46mm (max) 0 (min) 8 (max)
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aSC7512
M8 Package - 8-Lead MSOP Package Dimensions Pb-Free Package
0.525mm BSC 0.65mm BSC 9 (min) 15 (max)
Detail B
4.75mm (min) 5.05mm (max) 2.90mm (min) 3.10mm (max) 0.25mm (min) 0.40mm (max) 0 (min) 6 (max) 0.95mm BSC 0.13mm (min) 0.18mm (max) 0 (min) 6 (max) 0.40mm (min) 0.70mm (max)
Section A
0.13mm (min) 0.23mm (max)
Detail B
0.25mm (min) 0.35mm (max) 2.85mm (min) 3.05mm (max)
2.85mm (min) 3.05mm (max) 1.10mm (max)
0.78mm (min) 0.94mm (max)
A
A
0.10m m 0.25mm (min) 0.40mm (max) 2.90mm (min) 3.10mm (max) 0.05mm (min) 0.15mm (max)
2.90mm (min) 3.10mm (max) 4.75mm (min) 5.05mm (max)
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aSC7512
Data Sheet Classifications
Preliminary Specification
This classification is shown on the heading of each page of a specification for products that are either under development (design and qualification), or in the formative planning stages. Andigilog reserves the right to change or discontinue these products without notice.
New Release Specification
This classification is shown on the heading of the first page only of a specification for products that are either under the later stages of development (characterization and qualification), or in the early weeks of release to production. Andigilog reserves the right to change the specification and information for these products without notice.
Fully Released Specification Fully released datasheets do not contain any classification in the first page header. These documents contain specification on products that are in full production. Andigilog will not change any guaranteed limits without written notice to the customers. Obsolete datasheets that were written prior to January 1, 2001 without any header classification information should be considered as obsolete and non-active specifications, or in the best case as Preliminary Specifications.
PentiumTM is a trademark of Intel Corporation AthlonTM and DuronTM are trademarks of AMD Corporation
LIFE SUPPORT POLICY
ANDIGILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ANDIGILOG, INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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